| Opcode | Instruction | Op/En | 64-bit Mode | Compat/Leg Mode | Description |
|---|---|---|---|---|---|
| 0F BB /r | BTC r/m16, r16 | MR | Valid | Valid | Store selected bit in CF flag and complement. |
| 0F BB /r | BTC r/m32, r32 | MR | Valid | Valid | Store selected bit in CF flag and complement. |
| REX.W + 0F BB /r | BTC r/m64, r64 | MR | Valid | N.E. | Store selected bit in CF flag and complement. |
| 0F BA /7 ib | BTC r/m16, imm8 | MI | Valid | Valid | Store selected bit in CF flag and complement. |
| 0F BA /7 ib | BTC r/m32, imm8 | MI | Valid | Valid | Store selected bit in CF flag and complement. |
| REX.W + 0F BA /7 ib | BTC r/m64, imm8 | MI | Valid | N.E. | Store selected bit in CF flag and complement. |
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
| MR | ModRM:r/m (r, w) | ModRM:reg (r) | NA | NA |
| MI | ModRM:r/m (r, w) | imm8 | NA | NA |
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected bit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a register or an immediate value:
See also: Bit(BitBase, BitOffset) on page 3-10.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combina-tion with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset);
The CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF, AF, and PF flags are undefined.
| #GP(0) |
If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used but the destination is not a memory operand. |
| #GP | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS | If a memory operand effective address is outside the SS segment limit. |
| #UD | If the LOCK prefix is used but the destination is not a memory operand. |
| #GP(0) | If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. |
| #SS(0) | If a memory operand effective address is outside the SS segment limit. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made. |
| #UD | If the LOCK prefix is used but the destination is not a memory operand. |
Same exceptions as in protected mode.
| #SS(0) | If a memory address referencing the SS segment is in a non-canonical form. |
| #GP(0) | If the memory address is in a non-canonical form. |
| #PF(fault-code) | If a page fault occurs. |
| #AC(0) | If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. |
| #UD | If the LOCK prefix is used but the destination is not a memory operand. |